1. Technical Field
The present invention relates to an apparatus and a method for setting an operation mode in a DLL (Delay Locked Loop) circuit, and more particularly, to an apparatus and a method for setting an operation mode in a DLL circuit that is capable of reducing an erroneous operation.
2. Related Art
In general, a DLL circuit is used to generate an internal clock whose phase is a predetermined time earlier than a phase of a reference clock that is obtained by converting an external clock. In a semiconductor integrated circuit, such as a synchronous DRAM (SDRAM), which has relatively high integration, an internal clock operates in a state where it is synchronized with an external clock.
Specifically, the external clock is input to a clock input buffer through an input pin of the semiconductor integrated circuit. The clock input buffer outputs the internal clock. At this time, the internal clock has a phase that is delayed a predetermined time more than a phase of the external clock by the clock input buffer. The phase of the internal clock is further delayed by delay elements that are included in the semiconductor integrated circuit, and is transmitted to a data output buffer. Then, the internal clock controls the data output buffer to output data.
Accordingly, there is a problem in that the output data is delayed by a large amount of time, as compared with the external clock. That is, a phase of the external clock is staggered with one of the output data.
In order to solve this problem, the DLL circuit is used. The DLL circuit adjusts the phase of the internal clock to be earlier by a predetermined time than the phase of the external clock. Therefore, the output data is output without a delay compared with the external clock. That is, the DLL circuit receives the external clock and generates the internal clock whose phase is a predetermined time earlier than the phase of the external clock.
In the DLL circuit according to the related art, a reference clock is generated from a clock input buffer. The DLL circuit includes a replica delayer that is obtained by replicating a delay time existing in a path through which the reference clock is transmitted to the data output buffer, and generates a feedback clock. Then, the DLL circuit compares phases of the reference clock and the feedback clock and generates a signal according to the compared result. A delay line delays the reference clock in order to synchronize the phases of the reference clock and the feedback clock with each other.
At this time, as a method of locking a clock that applies a delay time to the reference clock, a coarse locking mode and a fine locking mode are used. According to the coarse locking mode, a delay time is applied by a plurality of unit delayers that are included in a delay line. According to the fine locking mode, a clock is minutely delayed by using a phase mixer instead of the unit delayer. In order to perform these operations, the DLL circuit includes an apparatus for setting an operation mode. The apparatus for setting an operation mode receives a phase comparing signal from a phase comparator that compares phases of the reference clock and the feedback clock, outputs a locking completion signal to instruct a timing of when the coarse locking mode is completed, thereby controlling the operation of the delay line.
FIG. 1 is a timing diagram illustrating the operation of an apparatus for setting an operation mode in a DLL circuit according to the related art. FIG. 1 shows a state where a phase of a phase comparing signal phcmp is changed according to a phase of a reference clock clk_ref and a phase of a feedback clock clk_fb delayed per operation period of the DLL circuit. In FIG. 1, the case is exemplified in which when the operation of the DLL circuit starts, the phase of the reference clock clk_ref is earlier than the phase of the feedback clock clk_fb. Hereinafter, the operation period of the DLL circuit is an interval between the time that a delay line receives the reference clock and the time that the delay line receives a delay control signal. The delay control signal is obtained by comparing phases of the reference clock and the feedback clock. The operation period of the DLL circuit is continuous.
Preferably, if the level of the reference clock clk_ref is at a high level at a rising edge time of the feedback clock clk_fb, the level of the phase comparing signal phcmp is at a high level. Then, if the feedback clock clk_fb is delayed for each operation period of the DLL circuit, accordingly the level of the reference clock clk_ref is at a low level at the rising edge time of the feedback clock clk_fb and the level of the phase comparing signal phcmp becomes a low level. If the level of the reference clock clk_ref is at a high level at the rising edge time of the feedback clock clk_fb after the several operation periods of the DLL circuit, the phase comparing signal phcmp becomes a high level again. When the level of the phase comparing signal phcmp is increased from the low level to the high level, the locking completion signal lock is enabled.
However, as shown in FIG. 1, the pulse width of the reference clock clk_ref may be increased due to any reason.
In this case, if the level of the reference clock clk_ref is at a high level at the rising edge time of the feedback clock clk_fb, the phase comparing signal phcmp becomes a high-level. In addition, if the level of the reference clock clk_ref becomes a low level at a rising edge time of the feedback clock clk_fb at a next operation period of the DLL circuit, the level of the phase comparing signal phcmp is changed to the low level. However, if the pulse width of the reference clock clk_ref is increased during a next operation period of the DLL circuit, it is determined that the level of the reference clock clk_ref is at a high level again at the rising edge time of the feedback clock clk_fb, and the level of the phase comparing signal phcmp is changed to a high level. Accordingly, the locking completion signal lock is enabled as a high level, and the coarse locking mode operation is completed.
As such, if the level of the phase comparing signal phcmp is changed from the low level to the high level, the apparatus for setting an operation mode in a DLL circuit recognizes that the coarse locking mode is completed, and enables the locking completion signal lock as a high level. That is, even when the phase of the feedback clock clk_fb and the phase of the reference clock clk_ref are different from each other by a ½ cycle, the coarse locking mode may be completed due to the change in a pulse width of the reference clock clk_ref.
Actually, as described above, the change in the pulse width of the reference clock is an erroneous operation that often occurs in the DLL circuit. The pulse width may be changed not only in the reference clock but also in the feedback clock. Further, an erroneous operation, such as a change in rising timing of the clock, often occurs. If the locking completion signal is enabled even when it is a predetermined timing, due to the erroneous operation, the semiconductor integrated circuit using the DLL circuit cannot perform the operation of synchronizing the clock and the data with each other.